LMK1D1212中文资料12 通道输出 1.8V、2.5V 和 3.3V LVDS 缓冲器数据手册TI规格书

描述 Description

The LMK1D1212 clock buffer distributes with minimum skew one of two selectable clock inputs (IN0, IN1) to 12 pairs of differential LVDS clock outputs (OUT0 through OUT11). Similarly, the LMK1D1216 distributes 16 pairs of differential LVDS clock outputs (OUT0 through OUT15). The LMK1D121x family can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, LP-HCSL, HCSL, CML, or LVCMOS.

The LMK1D121x is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin (see Figure 8-6).

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static low). The part supports a fail-safe function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 1.8-V or 2.5-V or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).

特性 Features

• High-performance LVDS clock buffer family: up to 2 GHz
• 2:16 differential buffer (LMK1D1216)
• Supply voltage: 1.71 V to 3.465 V
• Very low propagation delay:
• High-swing LVDS (boosted mode): 500-mV VOD typical when AMP_SEL = 1
• LVDS reference voltage, VAC_REF, available for capacitive-coupled inputs
• Packaged in
• LMK1D1216: 7-mm × 7-mm, 48-pin VQFN (RGZ)