LMK1D1208P中文资料8-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer with pin control数据手册TI规格书

描述 Description

The LMK1D1208P clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 8 pairs of differential LVDS clock outputs (OUT0 through OUT7) with minimum skew for clock distribution. The inputs can be either LVDS, LVPECL, LVCMOS, HCSL, or CML.

The LMK1D1208P is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin (see Figure 8-6). The IN_SEL pin selects the input which is routed to the outputs. The part supports a fail-safe input function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

Each LVDS differential output is enabled by setting the corresponding OEx pin to a logic high 1. If this pin is set to a logic low 0, the output is disabled in a Hi-Z state resulting in reduced power consumption.

The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).

特性 Features

• High-performance LVDS clock buffer family with 2 inputs and 8 outputs (2:8)
• Hardware pins for individual output enable/disable
• Low additive jitter: Very low phase noise floor: -164 dBc/Hz (typical)
• Very low propagation delay:
• Fail-safe inputs
• LVDS reference voltage, VAC_REF, available for capacitive-coupled inputs
• Packages available:
• 6-mm × 6-mm, 40-pin VQFN (RHA)

简介

LMK1D1208P属于集成电路（IC）的时钟缓冲器驱动器。由TI制造生产的LMK1D1208P时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。