丝印：LK05318B；Package：VQFN(RGZ)；LMK05318B Ultra-Low Jitter Clock Generator

1 Features • One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

文件：3.43581 Mbytes 页数：88 Pages

TI

德州仪器

丝印：LK05318B；Package：VQFN；LMK05318B Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

文件：3.51182 Mbytes 页数：87 Pages

TI

德州仪器

丝印：LK05318B；Package：VQFN(RGZ)；LMK05318B Ultra-Low Jitter Clock Generator

1 Features • One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

文件：3.43581 Mbytes 页数：88 Pages

TI

德州仪器

LMK05318B Ultra-Low Jitter Clock Generator

1 Features • One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

文件：3.43581 Mbytes 页数：88 Pages

TI

德州仪器

丝印：LK05318B；Package：VQFN(RGZ)；LMK05318B Ultra-Low Jitter Clock Generator

1 Features • One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

文件：3.43581 Mbytes 页数：88 Pages

TI

德州仪器

丝印：LK05318B；Package：VQFN(RGZ)；LMK05318B Ultra-Low Jitter Clock Generator

1 Features • One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

文件：3.43581 Mbytes 页数：88 Pages

TI

德州仪器

LMK05318B Ultra-Low Jitter Clock Generator

1 Features • One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

文件：3.43581 Mbytes 页数：88 Pages

TI

德州仪器

Package：48-VFQFN 裸露焊盘；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：ULTRA-LOW JITTER SINGLE CHANNEL

TI

德州仪器