丝印：LMK04610；Package：QFN(RTQ)；LMK04610 Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual-Loop PLLs

1 Features 1• Dual-loop PLL architecture • Ultra low noise (10 kHz to 20 MHz): – 48-fs RMS jitter at 1966.08 MHz – 50-fs RMS jitter at 983.04 MHz – 61-fs RMS jitter at 122.88 MHz • –165-dBc/Hz noise floor at 122.88 MHz • JESD204B support – Single shot, pulsed, and continuous SYSREF • 10 d

文件：2.5355 Mbytes 页数：132 Pages

TI

德州仪器

丝印：LMK04610；Package：QFN(RTQ)；LMK04610 Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual-Loop PLLs

1 Features 1• Dual-loop PLL architecture • Ultra low noise (10 kHz to 20 MHz): – 48-fs RMS jitter at 1966.08 MHz – 50-fs RMS jitter at 983.04 MHz – 61-fs RMS jitter at 122.88 MHz • –165-dBc/Hz noise floor at 122.88 MHz • JESD204B support – Single shot, pulsed, and continuous SYSREF • 10 d

文件：2.5355 Mbytes 页数：132 Pages

TI

德州仪器

丝印：LMK04610；Package：QFN(RTQ)；LMK04610 Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual-Loop PLLs

1 Features 1• Dual-loop PLL architecture • Ultra low noise (10 kHz to 20 MHz): – 48-fs RMS jitter at 1966.08 MHz – 50-fs RMS jitter at 983.04 MHz – 61-fs RMS jitter at 122.88 MHz • –165-dBc/Hz noise floor at 122.88 MHz • JESD204B support – Single shot, pulsed, and continuous SYSREF • 10 d

文件：2.5355 Mbytes 页数：132 Pages

TI

德州仪器

丝印：LMK04610；Package：QFN(RTQ)；LMK04610 Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual-Loop PLLs

1 Features 1• Dual-loop PLL architecture • Ultra low noise (10 kHz to 20 MHz): – 48-fs RMS jitter at 1966.08 MHz – 50-fs RMS jitter at 983.04 MHz – 61-fs RMS jitter at 122.88 MHz • –165-dBc/Hz noise floor at 122.88 MHz • JESD204B support – Single shot, pulsed, and continuous SYSREF • 10 d

文件：2.5355 Mbytes 页数：132 Pages

TI

德州仪器

丝印：LMK04610；Package：QFN(RTQ)；LMK04610 Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual-Loop PLLs

1 Features 1• Dual-loop PLL architecture • Ultra low noise (10 kHz to 20 MHz): – 48-fs RMS jitter at 1966.08 MHz – 50-fs RMS jitter at 983.04 MHz – 61-fs RMS jitter at 122.88 MHz • –165-dBc/Hz noise floor at 122.88 MHz • JESD204B support – Single shot, pulsed, and continuous SYSREF • 10 d

文件：2.5355 Mbytes 页数：132 Pages

TI

德州仪器

丝印：LMK04610；Package：QFN(RTQ)；LMK04610 Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual-Loop PLLs

1 Features 1• Dual-loop PLL architecture • Ultra low noise (10 kHz to 20 MHz): – 48-fs RMS jitter at 1966.08 MHz – 50-fs RMS jitter at 983.04 MHz – 61-fs RMS jitter at 122.88 MHz • –165-dBc/Hz noise floor at 122.88 MHz • JESD204B support – Single shot, pulsed, and continuous SYSREF • 10 d

文件：2.5355 Mbytes 页数：132 Pages

TI

德州仪器

丝印：LMK04610；Package：QFN(RTQ)；LMK04610 Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual-Loop PLLs

1 Features 1• Dual-loop PLL architecture • Ultra low noise (10 kHz to 20 MHz): – 48-fs RMS jitter at 1966.08 MHz – 50-fs RMS jitter at 983.04 MHz – 61-fs RMS jitter at 122.88 MHz • –165-dBc/Hz noise floor at 122.88 MHz • JESD204B support – Single shot, pulsed, and continuous SYSREF • 10 d

文件：2.5355 Mbytes 页数：132 Pages

TI

德州仪器

丝印：LMK04610；Package：QFN(RTQ)；LMK04610 Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual-Loop PLLs

1 Features 1• Dual-loop PLL architecture • Ultra low noise (10 kHz to 20 MHz): – 48-fs RMS jitter at 1966.08 MHz – 50-fs RMS jitter at 983.04 MHz – 61-fs RMS jitter at 122.88 MHz • –165-dBc/Hz noise floor at 122.88 MHz • JESD204B support – Single shot, pulsed, and continuous SYSREF • 10 d

文件：2.5355 Mbytes 页数：132 Pages

TI

德州仪器

丝印：LMK04610；Package：QFN(RTQ)；LMK04610 Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual-Loop PLLs

1 Features 1• Dual-loop PLL architecture • Ultra low noise (10 kHz to 20 MHz): – 48-fs RMS jitter at 1966.08 MHz – 50-fs RMS jitter at 983.04 MHz – 61-fs RMS jitter at 122.88 MHz • –165-dBc/Hz noise floor at 122.88 MHz • JESD204B support – Single shot, pulsed, and continuous SYSREF • 10 d

文件：2.5355 Mbytes 页数：132 Pages

TI

德州仪器

丝印：LMK04610；Package：QFN(RTQ)；LMK04610 Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual-Loop PLLs

1 Features 1• Dual-loop PLL architecture • Ultra low noise (10 kHz to 20 MHz): – 48-fs RMS jitter at 1966.08 MHz – 50-fs RMS jitter at 983.04 MHz – 61-fs RMS jitter at 122.88 MHz • –165-dBc/Hz noise floor at 122.88 MHz • JESD204B support – Single shot, pulsed, and continuous SYSREF • 10 d

文件：2.5355 Mbytes 页数：132 Pages

TI

德州仪器