丝印：LMK04110；Package：WQFN；LMK04100 Family Clock Jitter Cleaner with Cascaded PLLs

1FEATURES 23• Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO • Outputs – LVPECL/2VPECL, L

文件：926.89 Kbytes 页数：56 Pages

TI

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文件：162.11 Kbytes 页数：3 Pages

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文件：160.11 Kbytes 页数：3 Pages

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Silicon PNP epitaxial planar type

文件：83.79 Kbytes 页数：3 Pages

Panasonic

松下