LMK01000中文资料具有 3 个 LVDS 和 5 个 LVPECL 输出的 1.6GHz 高性能时钟缓冲器、分频器和分配器数据手册TI规格书

描述 Description

The LMK01000 family provides an easy way to divide and distribute high performance clock signals throughout the system. These devices provide best-in-class noise performance and are designed to be pin-to-pin and footprint compatible with LMK03000/LMK02000 family of precision clock conditioners.

The LMK01000 family features two programmable clock inputs (CLKin0 and CLKin1) that allow the user to dynamically switch between different clock domains.

Each device features 8 clock outputs with independently programmable dividers and delay adjustments. The outputs of the device can be easily synchronized by an external pin (SYNC*).

Target Applications

High performance Clock Distribution Wireless Infrastructure Medical Imaging Wired Communications Test and Measurement Military / Aerospace

特性 Features

• 30 fs additive jitter (100 Hz to 20 MHz)
• Programmable output channels (0 to 1600 MHz)
• Pin compatible family of clocking devices
• Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)
Device LVDS Outputs LVPECL Outputs LMK01000 3 5 LMK01010 8 0 LMK01020 0 8