LMK00804BQWRGTTQ1集成电路（IC）的时钟缓冲器驱动器规格书PDF中文资料

LMK00804BQWRGTTQ1属于集成电路（IC）的时钟缓冲器驱动器。由美国德州仪器公司制造生产的LMK00804BQWRGTTQ1时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。

1 Features

1• AEC-Q100 qualified with the following results:

– Device temperature grade 1: –40°C to +125°C,

TA

• Four LVCMOS/LVTTL outputs supporting 1.5-V to

3.3-V levels

– Additive jitter: 0.1-ps RMS (typical) at 40 MHz

– Noise floor: –168 dBc/Hz (typical) at 40 MHz

– Output frequency: 350 MHz (maximum)

– Output skew: 35 ps (maximum)

– Part-to-part skew: 550 ps (maximum)

• Two selectable inputs

– CLK_P, CLK_N pair accepts LVPECL, LVDS,

HCSL, SSTL, LVHSTL, or LVCMOS/LVTTL

– LVCMOS_CLK accepts LVCMOS/LVTTL

• Synchronous clock enable

• Core/output power supplies:

– 3.3 V/3.3 V

– 3.3 V/2.5 V

– 3.3 V/1.8 V

– 3.3 V/1.5 V

• Package: 16-pin VQFN

2 Applications

• Advanced Driver Assistance Systems (ADAS)

– Forward-facing long range radar

– Medium/short range radar

– Ultra short range radar

3 Description

The LMK00804B-Q1 is a high-performance clock fanout

buffer and level translator that can distribute up to

four LVCMOS/LVTTL outputs (3.3-V, 2.5-V, 1.8-V, or

1.5-V levels) from one of two selectable inputs that

can accept differential or single-ended inputs. The

clock enable input is synchronized internally to

eliminate runt or glitch pulses on the outputs when

the clock enable terminal is asserted or deasserted.

The outputs are held in logic low state when the clock

is disabled. The LMK00804B-Q1 can also distribute a

low-jitter clock across four transceivers and can

improve the overall target detection and resolution in

a cascaded mmWave radar system.