LM12458数据手册集成电路（IC）的ADC/DAC-特殊用途规格书PDF

描述 Description

The LM12458, and LM12H458 are highly integrated Data Acquisition Systems. Operating on just 5V, they combine a fully-differential self-calibrating (correcting linearity and zero errors) 13-bit (12-bit + sign) analog-to-digital converter (ADC) and sample-and-hold (S/H) with extensive analog functions and digital functionality. Up to 32 consecutive conversions, using two's complement format, can be stored in an internal 32-word (16-bit wide) FIFO data buffer. An internal 8-word RAM can store the conversion sequence for up to eight acquisitions through the LM12(H)458's eight-input multiplexer. The obsolete LM12454 has a four-channel multiplexer, a differential multiplexer output, and a differential S/H input. The LM12(H)458 can also operate with 8-bit + sign resolution and in a supervisory \"watchdog\" mode that compares an input signal against two programmable limits.

Programmable acquisition times and conversion rates are possible through the use of internal clock-driven timers. The reference voltage input can be externally generated for absolute or ratiometric operation or can be derived using the internal 2.5V bandgap reference.

All registers, RAM, and FIFO are directly addressable through the high speed microprocessor interface to either an 8-bit or 16-bit data bus. The LM12(H)458 includes a direct memory access (DMA) interface for high-speed conversion data transfer.

Additional applications information can be found in applications notes AN-906, AN-947 and AN-949.

Key Specifications(fCLK = 5 MHz; 8 MHz, H)

Resolution12-bit + sign or 8-bit + sign13-bit conversion time8.8 µs, 5.5 µs (H) (max)9-bit conversion time4.2 µs, 2.6 µs (H) (max)13-bit Through-put rate88k samples/s (min),140k samples/s (H) (min)Comparison time (\"watchdog\" mode)2.2 µs (max),1.4 µs (H) (max)ILE±1 LSB (max)VIN rangeGND to VA+Power Consumption30 mW, 34 mW (H) (max)Stand-by mode50 µW (typ)Single supply3V to 5.5V

The LM12458, and LM12H458 are highly integrated Data Acquisition Systems. Operating on just 5V, they combine a fully-differential self-calibrating (correcting linearity and zero errors) 13-bit (12-bit + sign) analog-to-digital converter (ADC) and sample-and-hold (S/H) with extensive analog functions and digital functionality. Up to 32 consecutive conversions, using two's complement format, can be stored in an internal 32-word (16-bit wide) FIFO data buffer. An internal 8-word RAM can store the conversion sequence for up to eight acquisitions through the LM12(H)458's eight-input multiplexer. The obsolete LM12454 has a four-channel multiplexer, a differential multiplexer output, and a differential S/H input. The LM12(H)458 can also operate with 8-bit + sign resolution and in a supervisory \"watchdog\" mode that compares an input signal against two programmable limits.

Programmable acquisition times and conversion rates are possible through the use of internal clock-driven timers. The reference voltage input can be externally generated for absolute or ratiometric operation or can be derived using the internal 2.5V bandgap reference.

All registers, RAM, and FIFO are directly addressable through the high speed microprocessor interface to either an 8-bit or 16-bit data bus. The LM12(H)458 includes a direct memory access (DMA) interface for high-speed conversion data transfer.

Additional applications information can be found in applications notes AN-906, AN-947 and AN-949.

Key Specifications(fCLK = 5 MHz; 8 MHz, H)

Resolution12-bit + sign or 8-bit + sign13-bit conversion time8.8 µs, 5.5 µs (H) (max)9-bit conversion time4.2 µs, 2.6 µs (H) (max)13-bit Through-put rate88k samples/s (min),140k samples/s (H) (min)Comparison time (\"watchdog\" mode)2.2 µs (max),1.4 µs (H) (max)ILE±1 LSB (max)VIN rangeGND to VA+Power Consumption30 mW, 34 mW (H) (max)Stand-by mode50 µW (typ)Single supply3V to 5.5V

特性 Features

• Three operating modes: 12-bit + sign, 8-bit + sign, and \"watchdog\"
• Single-ended or differential inputs
• Built-in Sample-and-Hold and 2.5V bandgap reference
• Instruction RAM and event sequencer
• 8-channel multiplexer
• 32-word conversion FIFO
• Programmable acquisition times and conversion rates
• Self-calibration and diagnostic mode
• 8- or 16-bit wide data bus microprocessor or DSP interface