OPERATIONAL AMPLIFIERS/BUFFERS

文件：451.19 Kbytes 页数：3 Pages

TI

德州仪器

12 x 12-bit Parallel Multiplier

DESCRIPTION The LMU112 is a high-speed, low power 12-bit parallel multiplier built using advanced CMOS technology. The LMU112 is pin and functionally compatible with Fairchilds’s MPY112K. FEATURES ❑ 25 ns Worst-Case Multiply Time ❑ Low Power CMOS Technology ❑ Replaces Fairchild MPY112K ❑ Two

文件：46.51 Kbytes 页数：6 Pages

LODEV

40 MHz Dual Clock Buffer

文件：975.5 Kbytes 页数：14 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

40 MHz Dual Clock Buffer

文件：1.28796 Mbytes 页数：19 Pages

TI

德州仪器