LH521028A中文资料夏普数据手册PDF规格书

FUNCTIONAL DESCRIPTION

The LH521028 is a high-speed 1,179,648-bit CMOS SRAM organized as 64K × 18. A fast, efficient design is obtained with a CMOS periphery and a matrix constructed with polysilicon load memory cells. The LH521028 is available in a compact 52-Pin PLCC, which along with the six pairs of supply terminals, provide for reliable operation.

FEATURES

• Fast Access Times: 15/17/20/25/35 ns

• Wide Word (18-Bits) for:

– Improved Performance

– Reduced Component Count

– Nine-bit Byte for Parity

• Transparent Address Latch

• Reduced Loading on Address Bus

• Low-Power Stand-by Mode when Deselected

• TTL Compatible I/O

• 5 V ± 10 Supply

• 2 V Data Retention

• JEDEC Standard Pinout

• Package: 52-Pin PLCC