ECP5™ and ECP5-5G™ Family

General Description The ECP5/ECP5-5G family of FPGA devices is optimized to deliver high performance features such as an enhanced DSP architecture, high speed SERDES (Serializer/Deserializer), and high speed source synchronous interfaces, in an economical FPGA fabric. This combination is achieved

文件：3.78907 Mbytes 页数：108 Pages

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莱迪思

ECP5™ and ECP5-5G™ Family

General Description The ECP5/ECP5-5G family of FPGA devices is optimized to deliver high performance features such as an enhanced DSP architecture, high speed SERDES (Serializer/Deserializer), and high speed source synchronous interfaces, in an economical FPGA fabric. This combination is achieved

文件：3.78907 Mbytes 页数：108 Pages

Lattice

莱迪思

ECP5™ and ECP5-5G™ Family

General Description The ECP5/ECP5-5G family of FPGA devices is optimized to deliver high performance features such as an enhanced DSP architecture, high speed SERDES (Serializer/Deserializer), and high speed source synchronous interfaces, in an economical FPGA fabric. This combination is achieved

文件：3.78907 Mbytes 页数：108 Pages

Lattice

莱迪思

ECP5™ and ECP5-5G™ Family

General Description The ECP5/ECP5-5G family of FPGA devices is optimized to deliver high performance features such as an enhanced DSP architecture, high speed SERDES (Serializer/Deserializer), and high speed source synchronous interfaces, in an economical FPGA fabric. This combination is achieved

文件：3.78907 Mbytes 页数：108 Pages

Lattice

莱迪思

ECP5™ and ECP5-5G™ Family

General Description The ECP5/ECP5-5G family of FPGA devices is optimized to deliver high performance features such as an enhanced DSP architecture, high speed SERDES (Serializer/Deserializer), and high speed source synchronous interfaces, in an economical FPGA fabric. This combination is achieved

文件：3.78907 Mbytes 页数：108 Pages

Lattice

莱迪思

ECP5™ and ECP5-5G™ Family

General Description The ECP5/ECP5-5G family of FPGA devices is optimized to deliver high performance features such as an enhanced DSP architecture, high speed SERDES (Serializer/Deserializer), and high speed source synchronous interfaces, in an economical FPGA fabric. This combination is achieved

文件：3.78907 Mbytes 页数：108 Pages

Lattice

莱迪思

ECP5™ and ECP5-5G™ Family

General Description The ECP5/ECP5-5G family of FPGA devices is optimized to deliver high performance features such as an enhanced DSP architecture, high speed SERDES (Serializer/Deserializer), and high speed source synchronous interfaces, in an economical FPGA fabric. This combination is achieved

文件：3.78907 Mbytes 页数：108 Pages

Lattice

莱迪思

ECP5™ and ECP5-5G™ Family

General Description The ECP5/ECP5-5G family of FPGA devices is optimized to deliver high performance features such as an enhanced DSP architecture, high speed SERDES (Serializer/Deserializer), and high speed source synchronous interfaces, in an economical FPGA fabric. This combination is achieved

文件：3.78907 Mbytes 页数：108 Pages

Lattice

莱迪思

FPGA和CPLD

投入更少，获得更多——ECP5和ECP5-5G器件相比竞争对手的FPGA产品成本低40%，使用更好的布线架构、双通道SERDES以及增强的DSP模块，减少高达4倍的乘法器资源使用，致力于为ASIC和ASSP提供互连。\n小尺寸封装，两倍功能密度——采用10x10 mm、0.5mm引脚间距封装，拥有高达85K LUT，并带有SERDES。适当地精简封装引脚，便于采用目前低成本的PCB布线技术。\n功耗降低30%——使用单通道SERDES时静态和动态功耗低于0.25W，使用四通道SERDES时功耗低于0.5W。 ●ECP5支持最高3.2 Gbps SERDES速率，ECP5-5G支持最高5 Gbps SERDES速率\n●器件拥有双通道模块，可提供最多4通道，实现更高的粒度\n●增强的DSP块为对称滤波器提供2倍的资源节约\n●单事件翻转（Single event upset, SEU）应对支持\n●可编程IO支持LVCMOS 33/25/18/15/12、XGMII、LVTTL、LVDS、Bus-LVDS、7:1 LVDS、LVPECL以及MIPI D-PHY输入接口;

Lattice

莱迪思

Package：256-LFBGA；包装：托盘 类别：集成电路（IC） FPGA（现场可编程门阵列） 描述：IC FPGA 197 I/O 256CABGA

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