LFCPNX-100-9CSG672A中文资料莱迪思数据手册PDF规格书

描述 Description

The CertusPro™-NX family of low-power general purpose FPGAs featuring 10G SerDes, LPDDR4 memory interface support and up to 100k logic cells can be used in a wide range of applications across multiple markets. It is built on the Lattice Nexus FPGA platform, using low-power 28 nm FD-SOI technology. It combines the extreme flexibility of an FPGA with the low power and high reliability (due to extremely low SER) of FD-SOI technology, and offers small footprint package options as well as 0.8 and 1.0 mm ball-pitch package options.

CertusPro-NX supports a variety of interfaces including PCI Express® (Gen1, Gen2, and Gen3), Ethernet (up to 10G), SLVS-EC, CoaXPress, eDP/DP, LVDS, Generic 8b10b, LVCMOS (0.9–3.3 V), and more.

Processing features of CertusPro-NX include up to 100k logic cells, 156 multipliers (18 × 18), 7.3 Mb of embedded memory (consisting of EBR and LRAM blocks), distributed memory and DRAM interfaces (supporting DDR3, DDR3L, LPDDR2, and LPDDR4 up to 1066 Mbps × 64bit data width).

CertusPro-NX FPGAs support fast configuration of the reconfigurable SRAM-based logic fabric, ultra-fast configuration of its programmable sysI/O™ and the TransFR™ field upgrade feature. Design security features, such as AES-256 encryption and ECDSA authentication, are also supported. In addition to the high reliability inherent to FD-SOI technology (due to its extremely low SER), active reliability features such as built-in frame-based Soft Error Detection (SED)/Soft Error Correction (SEC) (for SRAM-based logic fabric), and ECC (for EBR and LRAM) are also supported in CertusPro-NX devices. Dual 1 MSPS 12-bit Analog to Digital Convertors (ADCs) are available on-chip for system monitoring functions.

The Lattice Radiant™ design software allows large complex user designs to be efficiently implemented in CertusPro-NX FPGA family. Synthesis library support for CertusPro-NX devices is available for popular logic synthesis tools. Radiant tools use the synthesis tool output along with constraints from its floor planning tools to place and route the user design in CertusPro-NX device. The tools extract timing from the routing and back-annotate it into the design for timing verification.

Lattice provides many pre-engineered Intellectual Property (IP) modules for CertusPro-NX family. By using these configurable soft IP cores as standardized blocks, you are free to concentrate on the unique aspects of your design, increasing your productivity.

特性 Features

 Programmable architecture

 50k to 100k logic cells

 96 to 156 multipliers (18 × 18) in sysDSP™ blocks

 3.8 to 7.3 Mb of embedded memory (including EBR and LRAM)

 170 to 299 programmable sysI/O (High Performance and Wide Range I/O)

Programmable sysI/O designed to support wide variety of interfaces

 High Performance (HP) I/O supported on bottom I/O banks

 Supports up to 1.8 V VCCIO

 Mixed voltage support (1.0 V, 1.2 V, 1.5 V, and 1.8 V)

 High-speed differential up to 1.5 Gbps

 Supports LVDS, Soft D-PHY Transmitter (Tx)/Receiver (Rx), LVDS 7:1 Tx/Rx, SLVS Tx/Rx, subLVDS Rx

 Supports SGMII (Gb Ethernet):

 Two channels (Tx/Rx) at 1.25 Gbps

 Dedicated DDR3/DDR3L and LPDDR2/LPDDR3/LPDDR4 memory support with DQS logic, up to 1066 Mbps data rate and ×64bit data width

 Wide Range (WR) I/O supported on left, right, and top I/O Banks

 Supports up to 3.3 V VCCIO

 Mixed voltage support: 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V

 Programmable slew rate: slow, medium, and fast

 Controlled impedance mode

 Emulated LVDS support

 Hot Socketing Support

Embedded SerDes

 From 625 Mbps up to 10.3125 Gbps per channel, with up to 8 channels

 Multiple Protocol PCS support

 PCIe hard IP supports:

 Gen1, Gen2, and Gen3

 Endpoint and Root complex

 Multi-function up to four functions

 Up to four lanes

 Ethernet

 10GBASE-R at 10.3125 Gbps

 SGMII at 1.25 Gbps and 2.5 Gbps

 XAUI at 3.125 Gbps per lane

 SLVS-EC at 1.25 Gbps, 2.5 Gbps and 5 Gbps

 DP/eDP at 1.62 Gbps (RBR), 2.7 Gbps (HBR), 5.4 Gbps (HBR2) and 8.1 Gbps (HBR3)

 CoaXPress at 1.25 Gbps, 2.5 Gbps, 3.125 Gbps, 5 Gbps and 6.25 Gbps

 Generic 8b10b at multiple data rates

 SerDes-only mode allows direct 8-bit or 10-bit interface to FPGA logic

Power modes – Low Power mode and High Performance modes

 User selectable

 Low Power mode for power saving and/or thermal challenges

 High Performance mode for faster processing

Small footprint package options

 9 mm × 9 mm to 27 mm × 27 mm package size

Two channels of Clock Data Recovery (CDR) up to 1.25 Gbps to support SGMII on HP I/O

 CDR for Rx

 8b/10b decoding

 Independent Loss of Lock (LOL) detector for each CDR block

sysCLOCK™ analog PLLs

 Three in 50k LC, and four in 100k LC

 Six outputs per PLL

 Fractional N

 Programmable and dynamic phase control

 Support spread spectrum clocking

sysDSP enhanced DSP blocks

 Hardened pre-adder

 Dynamic shift for AI/ML support

 Four 18 × 18, eight 9 × 9, two 18 × 36, or 36 × 36 multipliers

 Advanced 18 × 36, two 18 × 18, or four 8 × 8 MAC per sysDSP blocks

Flexible memory resources

 Up to 3.7 Mb sysMEM™ Embedded Block RAM (EBR) available

 Programmable width

 Error Correction Coding (ECC)*

 First In First Out (FIFO)

 344 kbits to 639 kbits distributed RAM

 Large RAM Blocks

 0.5 Mbits per block

 Up to seven (3.5 Mbit total) per device

Internal bus interface support

 APB control bus

 AHB-Lite for data bus

 AXI4-streaming

Configuration – Fast, Secure

 SPI – ×1, ×2, ×4 up to 150 MHz

 Master and Slave SPI support

 JTAG

 I2C and I3C

 Ultrafast I/O configuration for instant-on support (using Early I/O Release feature)

 Less than 30 ms full device configuration for LFCPNX-100 device

Cryptographic engine

 Bitstream encryption – using AES-256

 Bitstream authentication – using ECDSA

 Hashing algorithms – SHA, HMAC

 True Random Number Generator

 AES 128/256 Encryption

Single Event Upset (SEU) Mitigation Support

 Extremely low Soft Error Rate (SER) due to FD-SOI technology

 Soft Error Detect – Embedded hard macro

 Soft Error Correction – Transparent to user design operation

 Soft Error Injection – Emulate SEU event to debug system error handling

Dual ADC – 1 MSPS, 12-bit Successive Approximation Register (SAR), with Simultaneous Sampling*

 Three Continuous-time Comparators System-level support

 IEEE 1149.1 and IEEE 1532 compliant

 Reveal Logic Analyzer

 On-chip oscillator for device initialization and general use

 1.0 V core power supply

*Available in Commercial/Industrial –8 and –9 speed grades and Automotive –7 and –8 speed grades.