LC78621E中文资料三洋数据手册PDF规格书

Overview

The LC78621E is a CMOS LSI that implements the signal processing and servo control required by compact disk players, laser disks, CD-V, CD-I and related products. The LC78621E provides several types of signal processing, including demodulation of the optical pickup EFM signal, de-interleaving, error detection and correction, and digital filters that can help reduce the cost of CD player units. It also processes a rich set of servo system commands sent from the control microprocessor. It also incorporates an EFM-PLL circuit and a one-bit D/A converter.

特性 Features

• 80-pin QIP (miniature, reduced space package)

• Silicon gate CMOS process (for low power)

• 5 V single-voltage power supply (for use in portable products)

Functions

• Input signal processing: The LC78621E takes an HF

signal as input, digitizes (slices) that signal at a precise

level, converts that signal to an EFM signal, and

generates a PLL clock with an average frequency of

4.3218 MHz by comparing the phases of that signal and

an internal VCO.

• Precise reference clock and necessary internal timing

generation using an external 16.9344 MHz crystal

oscillator

• Disk motor speed control using a frame phase difference

signal generated from the playback clock and the

reference clock

• Frame synchronization signal detection, protection and

interpolation to assure stable data readout

• EFM signal demodulation and conversion to 8-bit

symbol data

• Subcode data separation from the EFM demodulated

signal and output of that data to an external

microprocessor

• Subcode Q signal output to a microprocessor over the

serial I/O interface after performing a CRC error check

• Demodulated EFM signal buffering in internal RAM to

handle up to ±4 frames of disk rotational jitter

• Demodulated EFM signal reordering in the prescribed

order for data unscrambling and de-interleaving

• Error detection, correction, and flag processing (error

correction scheme: dual C1 plus dual C2 correction)

• The LC78620E sets the C2 flags based on the C1 flags

and a C2 check, and then performs signal interpolation

or muting depending on the C2 flags. The interpolation

circuit uses a quadruple interpolation scheme. The

output value converges to the muting level when four or

more consecutive C2 flags occur.

• Support for command input from a control

microprocessor: commands include track jump, focus

start, disk motor start/stop, muting on/off and track

count (8 bit serial input)

• Built-in digital output circuits.

• Arbitrary track counting to support high-speed data

access

• Zero cross muting

• Supports the implementation of a double-speed dubbing

function.

• D/A converter outputs with data continuity improved by

8× oversampling digital filters. (These filters function as

4× oversampling filters during double-speed playback.)

• Built-in third-order ∑∆ D/A converters (PWM output)

• Built-in digital attenuator (8 bits – alpha, 239 steps)

• Built-in digital de-emphasis

• Built-in digital level and peak meter functions

• Support for bilingual applications