LA9310中文资料恩XP数据手册PDF规格书

•The Layerscape® Access LA9310 signal processor contains one Arm® Cortex®-M4 processor with the following capabilities:

—Core speed of 307.2 MHz

—128 KB tightly coupled instruction memory

—64 KB tightly coupled data memory

•The LA9310 signal processor utilizes VSPA-16SP the 恩XP vector signal processing acceleration platform running at 614.4 MHz

—Forward error correction unit

—34 KB program memory

—32 KB data memory

•AXI i/q bridge (AXIQ)

•PHY Timer

•NIC 301 Interconnect running at 307.2 MHz (subpartitions at 614.4 MHz)

•ADC/DAC subsystem

—Four ADC with differential input for complex baseband i/q paths – eight differential pairs

—One DAC with differential output for complex baseband i/q paths – two differential pairs

—One ADC with single input for Tx detection: single input signal

•eDMA controller

•LLCP controller

•One SerDes lane for high-speed peripheral interfaces

—One PCI Express 3.0 controller (one supporting x1 operation)

•Additional peripheral interfaces include:

—One I2C controller, standard multi-drop multimaster 2-pin interface to external peripherals and EEPROMs. The second I2C module is completely internal to the device to interface with the ADC/DAC IP

—One general purpose single-lane serial peripheral interface (SPI) controller

—General purpose IO (GPIO)

—One UART controller, 62550 compatible 2-pin UART for debug console interface

—JTAG

—Debug support with run control

•157 FC-PBGA package, 8.0 mm x 8.0 mm, 0.5 mm pitch