L29C520PC22中文资料4 x 8-bit Multilevel Pipeline Register数据手册LOGIC Devices规格书

描述 Description

DESCRIPTION
The L29C520 and L29C521 are pin for-pin compatible with the IDT29FCT520/IDT29FCT521 and AMD Am29520/Am29521, implemented in low power CMOS.
The L29C520 and L29C521 contain four registers which can be configured as two independent, 2-level pipelines or as one 4-level pipeline.
The Instruction pins, I1-0, control the loading of the registers. For either device, the registers may be configured as a four-stage delay line, with data loaded into R1 and shifted sequentially through R2, R3, and R4. Also, for the L29C520, data may be loaded from the inputs into either R1 or R3 with only R2 or R4 shifting. The L29C521 differs from the L29C520 in that R2 and R4 remain unchanged during this type of data load, as shown in Tables 1 and 2. Finally, I1-0 may be set to prevent any register from changing.FEATURES
❑ Four 8-bit Registers
❑ Implements Double 2-Stage Pipeline or Single 4-Stage Pipeline Register
❑ Hold, Shift, and Load Instructions
❑ Separate Data In and Data Out Pins
❑ High-Speed, Low Power CMOS Technology
❑ Three-State Outputs
❑ Replaces IDT29FCT520/IDT29FCT521 and AMD Am29520/Am29521
❑ Package Styles Available:
  
• 24-pin PDIP
  
• 28-pin PLCC, J-Lead

特性 Features

❑ Four 8-bit Registers
❑ Implements Double 2-Stage Pipeline or Single 4-Stage Pipeline Register
❑ Hold, Shift, and Load Instructions
❑ Separate Data In and Data Out Pins
❑ High-Speed, Low Power CMOS Technology
❑ Three-State Outputs
❑ Replaces IDT29FCT520/IDT29FCT521 and AMD Am29520/Am29521
❑ Package Styles Available:
  
• 24-pin PDIP
  
• 28-pin PLCC, J-Lead