KS8695X开发板套件编程器的评估演示板及套件规格书PDF中文资料

General Description

The CENTAUR KS8695X, Multi-Port Gateway-on-a-Chip, delivers a new level of networking integration and

performance for accelerating broadband gateway development. Key components integrated in the KS8695X

include:

• Integrated Layer 2 managed switch with five Fast Ethernet transceivers and patented mixed-signal low

power technology, five media access control (MAC) units, a high-speed non-blocking switch fabric, a

dedicated address look-up engine, an on-chip frame buffer memory, and LED controls. One port is partitioned

for WAN interface with the other four ports for LAN access.

• A 166MHz ARM™ (ARM992T) processor with memory management unit (MMU) and 8KB I-cache and 8KB D

cache.

• XceleRouter™ technology for the WAN and LAN interfaces.

• Shared programmable 8/16/32-bit data bus and 22-bit address bus with up to 64MB total memory space for SDRAM, ROM, Flash, SRAM, and all peripheral devices.

• Other peripheral support logic including GPIO, a watchdog timer, an interrupt controller, and a JTAG

debugging interface.

Complete hardware and software reference designs are available.

The KS8695X represents a new level of total solution optimized for broadband gateway system development

and renders speedy routing performance and connectivity interfaces for value-added networking expansions.

特性 Features

•The CENTAUR KS8695X featuring XceleRouter tech nology is a single-chip multi-port gateway-on-a-chip with

all the key components integrated for a high-perfor mance and low-cost broadband gateway.

• ARM922T High-Performance CPU Core

– ARM922T core at 166MHz

– 8KB I-cache and 8KB D-cache

– Memory management unit (MMU) for Linux and WinCE®

– 32-bit ARM and 16-bit thumb instruction sets for smaller memory footprints

• XceleRouter Technology

– TCP/UDP/IP packet header checksum generation to offload CPU tasks

– IPv4 packet filtering on checksum errors

– Automatic error packet discard

• Integrated Ethernet Transceivers and Switch Engine

– Five 10/100 transceivers and five MACs (1P for WAN interface, 4P for LAN switching)

– 10BASE-T, 100BASE-TX, and 100BASE-FX modes (FX on the WAN port)

– On-chip SRAM as frame buffer memory

– Wire-speed switching

– VLAN ID and 802.1p tag/untag options

– Extensive MIB counter management support

– IGMP snooping for multicast packet filtering

– Port-based VLAN

– QoS/CoS packet prioritization support: per port, 802.1p and DiffServ-based

– 802.1D Spanning Tree Protocol support

– Dedicated 1K entry look-up engine

– Automatic MDI/MDI-X crossover on all ports

– Port mirroring/monitoring/sniffing

– Broadcast storm protection with control

– Full- and half-duplex flow control

• Memory and External I/O Interfaces

– 8/16/32-bit wide shared data path for SDRAM, ROM/SRAM/Flash and external I/O

– Total memory space up to 64MB

– Intel®/AMD®

-type Flash support

• WAN and LAN DMA Engines and FIFO

– DMA engine with burst mode support for efficient WAN and LAN data transfers

– FIFOs for back-to-back packet transfers

• Peripheral Support

– 8/16/32-bit external I/O interface supporting PCMCIA or generic CPU/DSP host I/F

– Eight general-purpose input/output (GPIO)

– Two 32-bit timer counters (one watchdog)

– Interrupt controller

– ARM922T JTAG debug interface

• Power Management

– Reduced CPU and system clock speeds

• System Design

– Up to 166MHz CPU and 125MHz bus speed

• Reference HW/SW Evaluation Kit

– Hardware evaluation board (passes class B EMI)

– Board support package including firmware source codes, linux kernel, and software stacks

– Documentation for design and programming

• Commercial Temperature Range: 0°C to +70°C

• Available in 208-Pin PQFP

Applications

• Multi-port broadband gateway

• Multi-port firewall and VPN appliances

• Combination wireless and wireline gateway

• Multi-port VoIP gateway

• Fiber-to-the-home managed CPE