KM732V596A中文资料三星数据手册PDF规格书

32Kx32-Bit Synchronous Pipelined Burst SRAM

GENERAL DESCRIPTION

The KM732V596A/L is a 1,048,576 bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based Mobile System.

The KM732V596A/L is fabricated using SAMSUNG¢s high performance CMOS technology and is available in a 100pin TQFP package. Multiple power and ground pins are utilized to minimize ground bounce.

FEATURES

• Synchronous Operation.

• 2 Stage Pipelined operation with 4 Burst.

• On-Chip Address Counter.

• Write Self-Timed Cycle.

• On-Chip Address and Control Registers.

• VDD=3.3V-5/+10 Power Supply for 3.3V I/O.

• VDD=3.3V±5 Power Supply for 2.5V I/O.

• I/O Supply Voltage : 3.3V-5/+10 for 3.3V I/O or 2.5V+0.4V/-0.13V for 2.5V I/O

• 5V Tolerant Inputs except I/O Pins.

• Byte Writable Function.

• Global Write Enable Controls a full bus-width write.

• Power Down State via ZZ Signal.

• Asynchronous Output Enable Control.

• ADSP, ADSC, ADV Burst Control Pins.

• LBO Pin allows a choice of either a interleaved burst or a linear burst.

• Three Chip Enables for simple depth expansion with No Data Contention ; 2cycle Enable, 1cycle Disable.

• TTL-Level Three-State Output.

• 100-TOFP-1420A