KM718FV4021中文资料三星数据手册PDF规格书

FUNCTION DESCRIPTION

The KM736FV4021 and KM718FV4021 are 4,718,592 bit Synchronous Pipeline Mode SRAM. It is organized as 131,072words of 36 bits(or 262, 144 words of 18 bits)and is implemented in SAMSUNG¢s advanced CMOS technology.

FEATURES

• 128Kx36 or 256Kx18 Organizations.

• 3.3V Core Power Supply.

• LVTTL Input and Output Levels.

• Differential, PECL Clock Inputs K, K.

• Synchronous Read and Write Operation

• Registered Input and Registered Output

• Internal Pipeline Latches to Support Late Write.

• Byte Write Capability(four byte write selects, one for each 9bits)

• Synchronous or Asynchronous Output Enable.

• Power Down Mode via ZZ Signal.

• JTAG 1149.1 Compatible Test Access port.

• 119(7x17)Pin Ball Grid Array Package(14mmx22mm)