Dual J-K Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS

文件：245.55 Kbytes 页数：6 Pages

KODENSHI

可天士

Dual J-K Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS

文件：245.55 Kbytes 页数：6 Pages

KODENSHI

可天士

Dual J-K Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS

文件：245.55 Kbytes 页数：6 Pages

KODENSHI

可天士

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

DESCRIPTION The M54HC112 is an high speed CMOS DUAL J-K FLIP-FLOP WITH PRESET AND CLEAR fabricated with silicon gate C2MOS technology. The M54HC112 dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs for each flip-flop. When the clock goes high, the inputs ar

文件：251.25 Kbytes 页数：11 Pages

STMICROELECTRONICS

意法半导体

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：409.81 Kbytes 页数：12 Pages

STMICROELECTRONICS

意法半导体

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：409.81 Kbytes 页数：12 Pages

STMICROELECTRONICS

意法半导体