K9HBG08U1M-I数据手册Samsung中文资料规格书

描述 Description

GENERAL DESCRIPTION
Offered in 2Gx8bit, the K9LAG08U0M is a 16G-bit NAND Flash Memory with spare 512M-bit. Its NAND cell provides the most cost effective solution for the solid state mass storage market. A program operation can be performed in typical 800µs on the 2,112-byte page and an erase operation can be performed in typical 1.5ms on a (256K+8K)byte block. Data in the data register can be read out at 30ns(K9MCG08U5M:50ns) cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9LAG08U0M′s extended reliability of 5K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9LAG08U0M is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.
An ultra high density solution having two 16Gb stacked with two chip selects is also available in standard TSOPI package.FEATURES
• Voltage Supply : 2.7 V ~ 3.6 V
• Organization
   - Memory Cell Array : (2G + 64M)bit x 8bit
   - Data Register : (2K + 64)bit x8bit
• Automatic Program and Erase
   - Page Program : (2K + 64)Byte
   - Block Erase : (256K + 8K)Byte
• Page Read Operation
   - Page Size : (2K + 64)Byte
   - Random Read : 60µs(Max.)
   - Serial Access : 30ns(Min.)
   *K9MCG08U5M : 50ns(Min.)
• Memory Cell : 2bit / Memory Cell
• Fast Write Cycle Time
   - Program time : 800µs(Typ.)
   - Block Erase Time : 1.5ms(Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
   - Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
   - Endurance : 5K Program/Erase Cycles(with 4bit/512byte ECC)
   - Data Retention : 10 Years
• Command Register Operation
• Unique ID for Copyright Protection
• Package :
   - K9LAG08U0M-PCB0/PIB0 : Pb-FREE PACKAGE
      48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
   - K9HBG08U1M-PCB0/PIB0 : Pb-FREE PACKAGE
      48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
   - K9HBG08U1M-ICB0/IIB0
      52 - Pin TLGA (12 x 17 / 1.0 mm pitch)
   - K9MCG08U5M-PCB0/PIB0 : Two K9HBG08U0M package stacked
      48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) : Pb-FREE PACKAGE

特性 Features

• Voltage Supply : 2.7 V ~ 3.6 V
• Organization
   - Memory Cell Array : (2G + 64M)bit x 8bit
   - Data Register : (2K + 64)bit x8bit
• Automatic Program and Erase
   - Page Program : (2K + 64)Byte
   - Block Erase : (256K + 8K)Byte
• Page Read Operation
   - Page Size : (2K + 64)Byte
   - Random Read : 60µs(Max.)
   - Serial Access : 30ns(Min.)
   *K9MCG08U5M : 50ns(Min.)
• Memory Cell : 2bit / Memory Cell
• Fast Write Cycle Time
   - Program time : 800µs(Typ.)
   - Block Erase Time : 1.5ms(Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
   - Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
   - Endurance : 5K Program/Erase Cycles(with 4bit/512byte ECC)
   - Data Retention : 10 Years
• Command Register Operation
• Unique ID for Copyright Protection
• Package :
   - K9LAG08U0M-PCB0/PIB0 : Pb-FREE PACKAGE
      48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
   - K9HBG08U1M-PCB0/PIB0 : Pb-FREE PACKAGE
      48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
   - K9HBG08U1M-ICB0/IIB0
      52 - Pin TLGA (12 x 17 / 1.0 mm pitch)
   - K9MCG08U5M-PCB0/PIB0 : Two K9HBG08U0M package stacked
      48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) : Pb-FREE PACKAGE