K7P161866A-HC25中文资料三星数据手册PDF规格书

FEATURES

• 512Kx36 or 1Mx18 Organizations.

• 2.5V Core/1.5V Output Power Supply (1.9V max VDDQ).

• HSTL Input and Output Levels.

• Differential, HSTL Clock Inputs K, K.

• Synchronous Read and Write Operation

• Registered Input and Registered Output

• Internal Pipeline Latches to Support Late Write.

• Byte Write Capability(four byte write selects, one for each 9bits)

• Synchronous or Asynchronous Output Enable.

• Power Down Mode via ZZ Signal.

• Programmable Impedance Output Drivers.

• JTAG 1149.1 Compatible Test Access port.

• 119(7x17)Pin Ball Grid Array Package(14mmx22mm).