K4T51163QB-ZCCC中文资料三星数据手册PDF规格书

DDR2 SDRAM

The 512Mb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x 4banks, 16Mbit x 8 I/Os x 4 banks or 8Mbit x 16 I/Os x 4 banks device. This synchronous device achieves high speed double

data-rate transfer rates of up to 533Mb/sec/pin (DDR2-533) for

general applications.

The chip is designed to comply with the following key DDR2 SDRAM features such as posted CAS with additive latency, write latency = read latency -1, Off-Chip Driver(OCD) impedance

adjustment and On Die Termination.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and Kfalling). All I/Os are synchronized with a pair ofbidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in a RAS/CASmultiplexing style. For example, 512Mb(x4) device receive 14/11/2 addressing.

The 512Mb DDR2 device operates with a single 1.8V ± 0.1V power supply and 1.8V ± 0.1V VDDQ.

The 512Mb DDR2 device is available in 60ball FBGAs(x4/x8) and in 84ball FBGAs(x16).

• JEDEC standard 1.8V ± 0.1V Power Supply

• VDDQ = 1.8V ± 0.1V

• 200 MHz fCKfor 400Mb/sec/pin, 267MHz fCKfor 533Mb/sec/pin

• 4 Banks

• Posted CAS

• Programmable CASLatency: 3, 4, 5

• Programmable Additive Latency: 0, 1 , 2 , 3 and 4

• Write Latency(WL) = Read Latency(RL) -1

• Burst Length: 4 , 8(Interleave/nibble sequential)

• Programmable Sequential / Interleave Burst Mode

• Bi-directional DifferentialData-Strobe (Single-ended data strobe is an optional feature)

• Off-Chip Driver(OCD) Impedance Adjustment

• On Die Termination

• Special Function Support

-High Temperature Self-Refresh rate enable

• Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE <95 °C

• Package: 60ball FBGA - 128Mx4/64Mx8 , 84ball FBGA - 32Mx16

• All of Lead-free products are compliant for RoHS