256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL

GENERAL DESCRIPTION The K4S561632D is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are p

文件：60.89 Kbytes 页数：11 Pages

Samsung

三星

256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL

GENERAL DESCRIPTION\nThe K4S561632D is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are pos • JEDEC standard 3.3V power supply\n• LVTTL compatible with multiplexed address\n• Four banks operation\n• MRS cycle with address key programs\n   -. CAS latency (2 & 3)\n   -. Burst length (1, 2, 4, 8 & Full page)\n   -. Burst type (Sequential & Interleave)\n• All inputs are sampled at the positive;

Samsung

三星

256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL

GENERAL DESCRIPTION The K4S561632D is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are p

文件：60.89 Kbytes 页数：11 Pages

Samsung

三星

TSOP-54

Samsung

三星

上传：深圳市凌旭科技有限公司

TSOP54

Samsung

三星

上传：深圳硅原半导体有限公司