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K4H640838M-TCB0中文资料三星数据手册PDF规格书
K4H640838M-TCB0规格书详情
Features
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM/DM for write masking only
• Auto & Self refresh
• 15.6us refresh interval(4K/64ms refresh)
• Maximum burst refresh cycle : 8
• 66pin TSOP II package
产品属性
- 型号:
K4H640838M-TCB0
- 制造商:
SAMSUNG
- 制造商全称:
Samsung semiconductor
- 功能描述:
128Mb DDR SDRAM
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
SAMSUNG |
23+ |
TSOP |
20000 |
原厂原装正品现货 |
询价 | ||
SAMSUNG |
2016+ |
TSSOP66P |
6523 |
只做原装正品现货!或订货! |
询价 | ||
SANSUNG |
23+ |
60FBGA |
1550 |
特价库存 |
询价 | ||
SAM |
21+ |
TSOP |
4000 |
只做原装正品,不止网上数量,欢迎电话微信查询! |
询价 | ||
SAMSUNG/三星 |
21+ |
TSOP |
10000 |
全新原装 公司现货 价格优 |
询价 | ||
- |
23+ |
NA |
13000 |
原厂授权一级代理,专业海外优势订货,价格优势、品种 |
询价 | ||
SAMSUNG/三星 |
2019 |
BGA |
55000 |
专营原装正品现货 |
询价 | ||
SAMSUNG/三星 |
19+ |
BGA |
24830 |
进口原装现货 |
询价 | ||
SAMSUNG/三星 |
23+ |
TSOP |
25000 |
代理原装现货,假一赔十 |
询价 | ||
SAM |
24+ |
TSOP66 |
598000 |
原装现货假一赔十 |
询价 |