512Mb G-die DDR SDRAM Specification

General Description The K4H510438G / K4H510838G / K4H511638G is 536,870,912 bits of double data rate synchronous DRAM organized as 4x 33,554,432 / 4x 16,777,216 / 4x 8,388,608 words by 4/8/16bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe al

文件：355.73 Kbytes 页数：24 Pages

SAMSUNG

三星

Consumer Memory

SDRAM Product Guide Memory Division November 2007

文件：542.54 Kbytes 页数：15 Pages

SAMSUNG

三星

512Mb G-die DDR SDRAM Specification

General Description The K4H510438G / K4H510838G / K4H511638G is 536,870,912 bits of double data rate synchronous DRAM organized as 4x 33,554,432 / 4x 16,777,216 / 4x 8,388,608 words by 4/8/16bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe al

文件：355.73 Kbytes 页数：24 Pages

SAMSUNG

三星

512Mb G-die DDR SDRAM Specification

General Description The K4H510438G / K4H510838G / K4H511638G is 536,870,912 bits of double data rate synchronous DRAM organized as 4x 33,554,432 / 4x 16,777,216 / 4x 8,388,608 words by 4/8/16bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe al

文件：355.73 Kbytes 页数：24 Pages

SAMSUNG

三星

512Mb G-die DDR SDRAM Specification

General Description The K4H510438G / K4H510838G / K4H511638G is 536,870,912 bits of double data rate synchronous DRAM organized as 4x 33,554,432 / 4x 16,777,216 / 4x 8,388,608 words by 4/8/16bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe al

文件：355.73 Kbytes 页数：24 Pages

SAMSUNG

三星

512Mb G-die DDR SDRAM Specification

General Description The K4H510438G / K4H510838G / K4H511638G is 536,870,912 bits of double data rate synchronous DRAM organized as 4x 33,554,432 / 4x 16,777,216 / 4x 8,388,608 words by 4/8/16bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe al

文件：355.73 Kbytes 页数：24 Pages

SAMSUNG

三星

128Mb DDR SDRAM

Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (

文件：669.27 Kbytes 页数：53 Pages

SAMSUNG

三星

128Mb DDR SDRAM

Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (

文件：669.27 Kbytes 页数：53 Pages

SAMSUNG

三星

128Mb DDR SDRAM

Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (

文件：669.27 Kbytes 页数：53 Pages

SAMSUNG

三星

128Mb DDR SDRAM

Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (

文件：669.27 Kbytes 页数：53 Pages

SAMSUNG

三星