K4G41325FE-HC25中文资料三星数据手册PDF规格书

1. FEATURES

• 1.5V + 0.045V power supply for device operations(VDD)

(Specific parts support 1.35V + 0.0405V)

• 1.5V + 0.045V power supply for I/O interface(VDDQ)

(Specific parts support 1.35V + 0.0405V)

• Maximum CK/CK up to 2.25GHz

• Maximum WCK/WCK up to 4.5GHz

• Maximum data rate up to 9.0Gbps/pin

• Halogen free 170 Ball FBGA(RoHS Compliant)

• Single ended interface for data, address and command

• Quarter data-rate differential clock inputs CK/CK for ADD/CMD

• Two half data-rate differential clock inputs WCK/WCK,

each associated with two data bytes(DQ, DBI, EDC)

• Double Data Rate (DDR) data (WCK)

• Single data rate (SDR) command (CK)

• Double data rate (DDR) addressing (CK)

• 16 internal banks for concurrent operation

• 4 bank groups for tCCDL 3 tCK and 4 tCK

• 8n prefetch architecture: 256bit per array read or write access

• Burst length: 8 only

• Programmable CAS latency:

• Programmable write latency :

• WRITE Data mask function via address bus

(single/double byte mask)

• Data bus inversion(DBI) and address bus inversion(ABI)

• Input/output PLL on/off mode

• Address training: Address input monitoring by DQ pins

• WCK2CK clock training with phase information by EDC pins

• Data read and write training via READ FIFO

• READ FIFO pattern preload by LDFF command

• Direct write data load to READ FIFO by WRTR command

• Consecutive read of READ FIFO by RDTR command

• Read/Write data transmission integrity secured by cyclic

redundancy check ; CRC-8(X8+X2+X+1) for EDC

• Read/write EDC on/off mode

• Programmable EDC hold pattern for CDR

• Programmable CRC read latency(CRCRL) range 0 to 3 tCK

• Programmable CRC write latency(CRCWL) range 7 to 14 tCK

• Low Power modes

• RDQS mode on EDC pin

• Auto & self refresh modes

• Auto precharge option for each burst access

• 32ms, auto refresh (16K cycles)

• On-die termination (ODT)

; Nominal values of 60ohm and 120ohm

• Pseudo open drain(POD-15) compatible inputs and outputs

; 40ohm pull down, 60ohm pull up

• ODT and output driver strength auto-calibration with external

resistor ZQ pin(120ohm)

• Programmable termination and driver strength offsets

• Output driver strength adjustment by MRS

• Selectable external or internal VREF for data inputs

;Programmable offsets for internal VREF

• Separate external VREF for address / command inputsdmd

• Vendor ID, FIFO depth and Density info fields for identification

• X32/X16 mode configuration set at power-up with EDC pin

• 16bits support for vendor ID/Density/FIFO depth MRS

• Mirror function with MF pin

• Boundary scan function with SEN pin