JM38510SLASH65352B2A.A中文资料德州仪器数据手册PDF规格书

1 Features

• Operating voltage range of 4.5 V to 5.5 V

• Outputs can drive up to 10 LSTTL loads

• Low power consumption, 40-μA max ICC

• Typical tpd = 17 ns

• ±4-mA output drive at 5 V

• Low input current of 1 μA max

• Inputs are TTL-voltage compatible

2 Description

The ’HCT74 devices contain two independent D-type

positive-edge-triggered flip-flops. A low level at the

preset (PRE) or clear (CLR) inputs sets or resets the

outputs, regardless of the levels of the other inputs.

When PRE and CLR are inactive (high), data at the

data (D) input meeting the setup time requirements

are transferred to the outputs on the positive-going

edge of the clock (CLK) pulse. Clock triggering occurs

at a voltage level and is not directly related to the

rise time of CLK. Following the hold-time interval, data

at the D input may be changed without affecting the

levels at the outputs.