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JM38510SLASH32502SRA中文资料德州仪器数据手册PDF规格书

JM38510SLASH32502SRA
厂商型号

JM38510SLASH32502SRA

功能描述

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

丝印标识

32502SRA

封装外壳

CDIP

文件大小

1.58154 Mbytes

页面数量

32

生产厂商

TI1

中文名称

德州仪器

网址

网址

数据手册

下载地址一下载地址二到原厂下载

更新时间

2025-8-23 10:05:00

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JM38510SLASH32502SRA规格书详情

Choice of Eight Latches or Eight D-Type

Flip-Flops in a Single Package

3-State Bus-Driving Outputs

Full Parallel Access for Loading

Buffered Control Inputs

Clock-Enable Input Has Hysteresis to

Improve Noise Rejection (’S373 and ’S374)

P-N-P Inputs Reduce DC Loading on Data

Lines (’S373 and ’S374)

description

These 8-bit registers feature 3-state outputs

designed specifically for driving highly capacitive

or relatively low-impedance loads. The

high-impedance 3-state and increased

high-logic-level drive provide these registers with

the capability of being connected directly to and

driving the bus lines in a bus-organized system

without need for interface or pullup components.

These devices are particularly attractive for

implementing buffer registers, I/O ports,

bidirectional bus drivers, and working registers.

The eight latches of the ’LS373 and ’S373 are

transparent D-type latches, meaning that while

the enable (C or CLK) input is high, the Q outputs

follow the data (D) inputs. When C or CLK is taken

low, the output is latched at the level of the data

that was set up.

The eight flip-flops of the ’LS374 and ’S374 are

edge-triggered D-type flip-flops. On the positive

transition of the clock, the Q outputs are set to the

logic states that were set up at the D inputs.

Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design

as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered

output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic

levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines

significantly.

OC does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new

data can be entered, even while the outputs are off.

供应商 型号 品牌 批号 封装 库存 备注 价格
TELEDYNE
专业铁帽
600
原装铁帽专营,代理渠道量大可订货
询价
TI/德州仪器
23+
DIP14
50000
全新原装正品现货,支持订货
询价
BOURNS/伯恩斯
23+
13000
原厂授权一级代理,专业海外优势订货,价格优势、品种
询价
TELEDYNE
CAN8
6500
一级代理 原装正品假一罚十价格优势长期供货
询价
VRN
23+
65480
询价
HI-G
8838
TO-5
50
普通
询价
TELEDYNE
20+
原装
67500
原装优势主营型号-可开原型号增税票
询价
TI
23+
N/A
7000
询价
BOURNS
18+
DIP3
12500
全新原装正品,本司专业配单,大单小单都配
询价
FOXCONN
24+
原厂封装
3000
原装现货假一罚十
询价