IWR6843AOP数据手册开发板套件编程器的射频评估开发套件开发板规格书PDF

描述 Description

The IWR6843AOP is an Antenna-on-Package (AOP) device that is an evolution within the single-chip radar device family from Texas Instruments (TI). This device enables unprecedented levels of integration in an extremely small form factor and is an ideal solution for low power, self-monitored, ultra-accurate radar systems in the industrial space.

特性 Features

• FMCW transceiver
• Integrated 4 receivers and 3 transmitters Antennas-On-Package (AOP)
• Integrated PLL, transmitter, receiver, Baseband, and ADC
• 60- to 64-GHz coverage with 4-GHz continuous bandwidth
• Supports 6-bit phase shifter for TX Beam forming
• Ultra-accurate chirp engine based on fractional-N PLL

• Built-in calibration and self-test
• ARM Cortex-R4F-based radio control system
• Built-in firmware (ROM)
• Self-calibrating system across frequency and temperature
• Embedded self-monitoring with no host processor involvement on Functional Safety-Compliant targeted devices

• C674x DSP for advanced signal processing
• Memory compression
• Hardware accelerator for FFT, filtering, and CFAR processing
• ARM-R4F microcontroller for object detection, and interface control
• Supports autonomous mode (loading user application from QSPI flash memory)

• Internal memory with ECC
• 1.75 MB, divided into MSS program RAM (512 KB), MSS data RAM (192 KB), DSP L1 RAM (64KB) and L2 RAM (256 KB), and L3 radar data cube RAM (768 KB)
• Technical reference manual includes allowed size modifications

• Other interfaces available to user application
• Up to 6 ADC channels (low sample rate monitoring)
• Up to 2 SPI ports
• Up to 2 UARTs
• 1 CAN-FD interface
• I2C
• GPIOs
• 2 lane LVDS interface for raw ADC data and debug instrumentation

• Functional Safety-Compliant targeted
• Developed for functional safety applications
• Documentation will be available to aid IEC 61508 functional safety system design
• Hardware integrity up to SIL-2 targeted
• Safety-related certification IEC 61508 certification by TUV Sud planned

• Power management
• Built-in LDO network for enhanced PSRR
• I/Os support dual voltage 3.3 V/1.8 V

• Clock source
• 40.0 MHz crystal with internal oscillator
• Supports external oscillator at 40 MHz
• Supports externally driven clock (square/sine) at 40 MHz

• Easy hardware design
• 0.8-mm pitch, 180-pin 15 mm × 15 mm FCBGA package (ALP) for easy assembly and low-cost PCB design
• Small solution size

• Operating conditions:
• Junction temperature range of –40°C to 105°C