ISPLSI2032E中文资料莱迪思数据手册PDF规格书

描述 Description

The ispLSI 2032E is a High Density Programmable Logic Device. The device contains 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2032E features 5V in-system programmability and in-system diagnostic capabilities. The ispLSI 2032E offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems.

特性 Features

• SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC

— 1000 PLD Gates

— 32 I/O Pins, Two Dedicated Inputs

— 32 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— 100 Functionally and JEDEC Upward Compatible with ispLSI 2032 Devices

• HIGH PERFORMANCE E2CMOS® TECHNOLOGY

— fmax = 225 MHz Maximum Operating Frequency

— tpd = 3.5 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— 5V Programmable Logic Core

— ispJTAG™ In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port

— User-Selectable 3.3V or 5V I/O (48-Pin Package Only) Supports Mixed Voltage Systems

— PCI Compatible Outputs (48-Pin Package Only)

— Open-Drain Output Option

— Electrically Erasable and Reprogrammable

— Non-Volatile

— Unused Product Term Shutdown Saves Power

• ispLSI OFFERS THE FOLLOWING ADDED FEATURES

— Increased Manufacturing Yields, Reduced Time-to Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue Logic and Structured Designs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global Interconnectivity