In-System Programmable High Density PLD

Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.

文件：236.85 Kbytes 页数：16 Pages

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.

文件：236.85 Kbytes 页数：16 Pages

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 1032/883 is a High-Density Programmable Logic Device processed in full compliance to MIL-STD-883. This military grade device contains 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP p

文件：151.11 Kbytes 页数：12 Pages

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.

文件：236.85 Kbytes 页数：16 Pages

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.

文件：236.85 Kbytes 页数：16 Pages

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI 1032/883 is a High-Density Programmable Logic Device processed in full compliance to MIL-STD-883. This military grade device contains 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP p

文件：151.11 Kbytes 页数：12 Pages

Lattice

莱迪思

High-Density Programmable Logic

文件：256.36 Kbytes 页数：19 Pages

Lattice

莱迪思

High-Density Programmable Logic

文件：256.36 Kbytes 页数：19 Pages

Lattice

莱迪思

In-System Programmable High Density PLD

Lattice

莱迪思