ISP1161A1数据手册恩XP中文资料规格书
ISP1161A1规格书详情
描述 Description
General description
The ISP1161A1 is a single-chip Universal Serial Bus (USB) Host Controller (HC) and Device Controller (DC). The Host Controller portion of the ISP1161A1 complies with Universal Serial Bus Specification Rev. 2.0,supporting data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). The Device Controller portion of the ISP1161A1 also complies withUniversal Serial Bus Specification Rev. 2.0, supporting data transfer at full-speed (12 Mbit/s). These two USB controllers, the HC and the DC, share the same microprocessor bus interface. They have the same data bus, but different I/O locations. They also have separate interrupt request output pins,
separate DMA channels that include separate DMA request output pins and DMA acknowledge input pins. This makes it possible for a microprocessor to control both the USB HC and the USB DC at the same time.
特性 Features
■Complies withUniversal Serial Bus Specification Rev. 2.0
■The Host Controller portion of the ISP1161A1 supports data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
■The Device Controller portion of the ISP1161A1 supports data transfer at full-speed (12 Mbit/s)
■Combines the HC and the DC in a single chip
■On-chip DC complies with most USB device class specifications
■Both the HC and the DC can be accessed by an external microprocessor via separate I/O port addresses
■Selectable one or two downstream ports for the HC and one upstream port for the DC
■High-speed parallel interface to most of the generic microprocessors and Reduced Instruction Set Computer (RISC) processors such as:
◆Hitachi® SuperH™ SH-3 and SH-4
◆MIPS-based™ RISC
◆ARM7™, ARM9™, StrongARM®
■Maximum 15 Mbyte/s data transfer rate between the microprocessor and the HC, 11.1 Mbyte/s data transfer rate between the microprocessor and the DC
■Supports single-cycle and burst mode DMA operations
■Up to 14 programmable USB endpoints with 2 fixed control IN/OUT endpoints for the DC
■Built-in separate FIFO buffer RAM for the HC (4 kbytes) and DC (2462 bytes)
■Endpoints with double buffering to increase throughput and ease real-time data transfer for both DC transfers and HC isochronous (ISO) transactions
■6 MHz crystal oscillator with integrated PLL for low EMI
■Controllable LazyClock (100 kHz±50 %) output during ‘suspend’
■Clock output with programmable frequency (3 MHz to 48 MHz)
■Software controlled connection to USB bus (SoftConnect) on upstream port for the DC
■Good USB connection indicator that blinks with traffic (GoodLink) for the DC
■Software selectable internal 15 kΩpull-down resistors for HC downstream ports
■Dedicated pins for suspend sensing output and wake-up control input for flexible applications
■Global hardware reset input pin and separate internal software reset circuits for HC and DC
■Operation from a 5 V or a 3.3 V power supply
■Operating temperature range−40°Cto+85°C
■Available in two LQFP64 packages (SOT314-2 and SOT414-1).Applications
■Personal Digital Assistant (PDA)
■Digital camera
■Third-generation (3-G) phone
■Set-Top Box (STB)
■Information Appliance (IA)
■Photo printer
■MP3 jukebox
■Game console.
技术参数
- 型号:
ISP1161A1
- 功能描述:
USB 接口集成电路 USB1.1 HOST &DEVICE
- RoHS:
否
- 制造商:
Cypress Semiconductor
- 产品:
USB 2.0
- 接口类型:
SPI
- 工作电源电压:
3.15 V to 3.45 V
- 最大工作温度:
+ 85 C
- 安装风格:
SMD/SMT
- 封装/箱体:
WLCSP-20
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
PHI |
20+ |
QFP |
35830 |
原装优势主营型号-可开原型号增税票 |
询价 | ||
STE |
23+ |
NA |
32000 |
专业电子元器件供应链正迈科技特价代理特价,原装元器件供应,支持开发样品 |
询价 | ||
PHI |
24+/25+ |
35 |
原装正品现货库存价优 |
询价 | |||
PHILIP |
23+ |
14+ |
35478 |
##公司主营品牌长期供应100%原装现货可含税提供技术 |
询价 | ||
恩XP |
21+ |
QFP64 |
1398 |
只做原装正品,不止网上数量,欢迎电话微信查询! |
询价 | ||
恩XP |
25+ |
25000 |
原厂原包 深圳现货 主打品牌 假一赔百 可开票! |
询价 | |||
PHI |
25+ |
QFP48 |
3200 |
全新原装、诚信经营、公司现货销售 |
询价 | ||
恩XP |
24+ |
TQFP |
2650 |
原装优势!绝对公司现货 |
询价 | ||
PHI |
2015+ |
SMD/DIP |
19889 |
一级代理原装现货,特价热卖! |
询价 | ||
PHI |
2016+ |
QFP64 |
6523 |
只做原装正品现货!或订货! |
询价 |