ISL88022中文资料Triple Voltage Monitor with Adjustable Power-On Reset and Undervoltage/Overvoltage Monitoring Capability数据手册Renesas规格书

描述 Description

The ISL88021 and ISL88022 family of devices are customizable triple voltage-monitoring supervisors that assert a reset if any of the monitored voltages becomes non-compliant. They offer popular functions such as Power-On-Reset timing control with both RESET and RESET outputs, Supply Voltage Supervision, both under or overvoltage detection, and Manual Reset assertion. By offering these features in a small 8 Ld MSOP package, the ISL88021 and ISL88022 can lower system cost, reduce board space requirements and increase the reliability of systems. Applying a voltage to VDD activates the Power-On-Reset circuit which holds RESET low for an adjustable period of time. This allows the power supply and system oscillator to stabilize before the processor can execute code. Low VDD detection circuitry protects the user's system from low voltage conditions, resetting the system when VDD falls below its minimum preset voltage threshold VTH1. Reset remains asserted until VDD returns to its proper operating level and stabilizes. Two additional voltage monitoring inputs, V2MON (preset) and V3MON (adjustable), monitor other supplies to provide reliable system operation. The ISL88021 V3MON input monitors for undervoltage (UV) conditions whereas the ISL88022 V3MON input allows monitoring for overvoltage (OV) conditions. The monitored voltage on V3MON on either device is compared via a resistor divider to a 600mV internal reference. Hence, any voltage more or less positive than this reference can be accurately monitored to meet specific system level requirements or to fine-tune the threshold for applications requiring higher precision. These devices also let users increase the Power-On-Reset time-out delay by connecting a capacitor between CPOR and ground. This lengthens the period of an internal clock counter thereby increasing the time between voltage compliance and reset outputs signaling. A manual reset input provides debounce circuitry for minimum reset component count.

特性 Features

• Triple Voltage Monitor and Reset Assertion
• Low VDD Detection and Reset Assertion
• Adjustable Reset Threshold Voltages
• 0.6V ±6mV Over -40°C to +85°C
• Reset Signal Valid to VDD = 1V
• 140ms Minimum Reset Pulse Delay that is Customizable Using an External Capacitor
• Both RST and RST Outputs Available
• Undervoltage/Overvoltage Monitoring Capability
• Low 20µA Consumption
• Small 8 Ld MSOP Package
• Pb-Free Plus Anneal Available (RoHS Compliant)

应用 Application

• Altera FPGA Power
• Xilinx FPGA Power