IS67WVH64M8EALL-200BLA2中文资料矽成半导体数据手册PDF规格书

特性 Features

HyperBusTM Low Signal Count Interface

◼ 1.7 to 2.0V (1.8V typ.) and 2.7 to 3.6V (3.0 V

typ.) interface support

◼ Single-ended clock (CK) – 11 bus signals

◼ Optional differential clock (CK, CK#) – 12 bus

signals

◼ Chip Select (CS#)

◼ 8-bit data bus (DQ [7:0])

◼ Hardware reset (RESET#)

◼ Bidirectional Read-Write Data Strobe (RWDS)

– Output at the start of all transactions to indicate

refresh latency

– Output during read transactions as Read Data

Strobe

– Input during write transactions as Write Data

Mask

High Performance

◼ 250MHz (1.8V)/200MHz(3.0V) maximum clock

rate

◼ Double-Data Rate (DDR) - two data transfers

per clock

◼ Data throughput up to

500MBps(1.8V)/400MBps(3.0V)

◼ Configurable Burst Characteristics

- Wrapped burst lengths:

o 16 bytes (8 clocks)

o 32 bytes (16 clocks)

o 64 bytes (32 clocks)

o 128 bytes (64 clocks)

– Linear burst

– Hybrid burst - one wrapped burst followed by

linear burst

– Wrapped or linear burst type selected in

each transaction

– Configurable output drive strength

◼ Configurable output drive strength

◼ Power modes

– Hybrid Sleep mode

– Deep Power Down

◼ Memory array refresh

– Partial array (1/8, 1/4, 1/2, and so on)

– Full array

◼ Temperature Grade

– Industrial: -40°C to +85°C

– Auto (A1) Grade: -40°C to +85°C

– Auto (A2) Grade: -40°C to +105°C

◼ Package

o 24-ball FBGA

o Green Package (RoHS Compliant,

Halogen-Free) and TSCA Compliant