1M x 36, 2M x 18 36 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

文件：1.55485 Mbytes 页数：33 Pages

ISSI

矽成半导体

1M x 36, 2M x 18 36 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

文件：1.55485 Mbytes 页数：33 Pages

ISSI

矽成半导体

1M x 36, 2M x 18 36 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

文件：1.55485 Mbytes 页数：33 Pages

ISSI

矽成半导体

1M x 36, 2M x 18 36 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

文件：1.55485 Mbytes 页数：33 Pages

ISSI

矽成半导体

1M x 36, 2M x 18 36 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

文件：1.55485 Mbytes 页数：33 Pages

ISSI

矽成半导体

1M x 36, 2M x 18 36 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

文件：1.55485 Mbytes 页数：33 Pages

ISSI

矽成半导体

静态随机存取存储器 36Mb, 7.5ns, 3.3V 1024K x 36 Sync 静态随机存取存储器

ISSI

矽成半导体

静态随机存取存储器 36Mb, 7.5ns, 3.3V 1024K x 36 Sync 静态随机存取存储器

ISSI

矽成半导体

Package：100-LQFP；包装：卷带（TR） 类别：集成电路（IC） 存储器 描述：IC SRAM 36MBIT PARALLEL 100LQFP

ISSI, Integrated Silicon Solution Inc

Package：100-LQFP；包装：托盘 类别：集成电路（IC） 存储器 描述：IC SRAM 36MBIT PARALLEL 100LQFP

ISSI, Integrated Silicon Solution Inc