IS61VVPS409618B-166M3L中文资料矽成半导体数据手册PDF规格书

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

• Three chip enable option for simple depth expansion

and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Single cycle deselect

• Snooze MODE for reduced-power standby

• JTAG Boundary Scan for PBGA package

• Power Supply

LPS: Vdd 3.3V (+ 5%), Vddq 3.3V/2.5V (+ 5%)

VPS: Vdd 2.5V (+ 5%), Vddq 2.5V (+ 5%)

VVPS: Vdd 1.8V (+ 5%), Vddq 1.8V (+ 5%)

• JEDEC 100-Pin TQFP, 119-ball PBGA, and

165-ball PBGA packages

• Lead-free available