1M x 36, 1M x 32, 2M x 18 36 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

文件：1.30333 Mbytes 页数：35 Pages

ISSI

矽成半导体

1M x 36, 1M x 32, 2M x 18 36 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

文件：1.30333 Mbytes 页数：35 Pages

ISSI

矽成半导体

1M x 36, 1M x 32, 2M x 18 36 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

文件：1.30333 Mbytes 页数：35 Pages

ISSI

矽成半导体

1M x 36, 1M x 32, 2M x 18 36 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

文件：1.30333 Mbytes 页数：35 Pages

ISSI

矽成半导体