IS61VPD51236B中文资料矽成半导体数据手册PDF规格书

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

• control

• Burst sequence control using MODE input

• Three chip enable option for simple depth expansion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Double cycle deselect

• Snooze MODE for reduced-power standby

• JEDEC 100-pin QFP, 165-ball BGA and 119-ball BGA packages

• Power supply:

LPD: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)

VPD: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)

VVPD: VDD 1.8V (± 5%), VDDQ 1.8V (± 5%)

• JTAG Boundary Scan for BGA packages

• Commercial, Industrial and Automotive temperature support

• Lead-free available

• For leaded options, please contact ISSI