4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM

FEATURES  2Mx36 and 4Mx18 configuration available.  On-chip Delay Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface fo

文件：929.31 Kbytes 页数：33 Pages

ISSI

矽成半导体

4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM

FEATURES  2Mx36 and 4Mx18 configuration available.  On-chip Delay Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface fo

文件：929.31 Kbytes 页数：33 Pages

ISSI

矽成半导体

4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM

FEATURES  2Mx36 and 4Mx18 configuration available.  On-chip Delay Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface fo

文件：929.31 Kbytes 页数：33 Pages

ISSI

矽成半导体

4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM

FEATURES  2Mx36 and 4Mx18 configuration available.  On-chip Delay Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface fo

文件：929.31 Kbytes 页数：33 Pages

ISSI

矽成半导体