4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM

FEATURES  2Mx36 and 4Mx18 configuration available.  On-chip Delay Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface fo

文件：917.73 Kbytes 页数：33 Pages

ISSI

矽成半导体

4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM

FEATURES  2Mx36 and 4Mx18 configuration available.  On-chip Delay Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface fo

文件：917.73 Kbytes 页数：33 Pages

ISSI

矽成半导体

4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM

FEATURES  2Mx36 and 4Mx18 configuration available.  On-chip Delay Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface fo

文件：917.73 Kbytes 页数：33 Pages

ISSI

矽成半导体

4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM

FEATURES  2Mx36 and 4Mx18 configuration available.  On-chip Delay Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface fo

文件：917.73 Kbytes 页数：33 Pages

ISSI

矽成半导体

4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM

FEATURES  2Mx36 and 4Mx18 configuration available.  On-chip Delay Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface fo

文件：917.73 Kbytes 页数：33 Pages

ISSI

矽成半导体

4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM

FEATURES  2Mx36 and 4Mx18 configuration available.  On-chip Delay Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface fo

文件：917.73 Kbytes 页数：33 Pages

ISSI

矽成半导体

2Mx36 and 4Mx18 configuration available

文件：920.47 Kbytes 页数：33 Pages

ISSI

矽成半导体

2Mx36 and 4Mx18 configuration available

文件：920.47 Kbytes 页数：33 Pages

ISSI

矽成半导体

QUADP SRAM

·18Mb, 36Mb, and 72Mb densities available\n·x18 and x36 configurations available\n·Burst of 2 or Burst of 4\n·Commercial and Industrial Temperature support\n·333MHz speed for QUAD and DDR-II\n·550MHz speed for QUADP and DDR-IIP\n·ODT and QVLD features for QUADP and DDR-IIP\n·Long-term Support

ISSI

矽成半导体

Package：165-LBGA；包装：托盘 类别：集成电路（IC） 存储器 描述：IC SRAM 72MBIT PARALLEL 165LFBGA

ISSI, Integrated Silicon Solution Inc