2Mx18, 1Mx36 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM

FEATURES  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface fo

文件：879.06 Kbytes 页数：33 Pages

ISSI

矽成半导体

2Mx18, 1Mx36 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM

FEATURES  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface fo

文件：879.06 Kbytes 页数：33 Pages

ISSI

矽成半导体

2Mx18, 1Mx36 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM

FEATURES  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface fo

文件：879.06 Kbytes 页数：33 Pages

ISSI

矽成半导体

2Mx18, 1Mx36 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM

FEATURES  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface fo

文件：879.06 Kbytes 页数：33 Pages

ISSI

矽成半导体

2Mx18, 1Mx36 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM

FEATURES  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface fo

文件：879.06 Kbytes 页数：33 Pages

ISSI

矽成半导体

2Mx18, 1Mx36 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM

FEATURES  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface fo

文件：879.06 Kbytes 页数：33 Pages

ISSI

矽成半导体

2Mx18, 1Mx36 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM

FEATURES  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface fo

文件：879.06 Kbytes 页数：33 Pages

ISSI

矽成半导体

2Mx18, 1Mx36 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM

FEATURES  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface fo

文件：879.06 Kbytes 页数：33 Pages

ISSI

矽成半导体

2Mx18, 1Mx36 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM

FEATURES  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface fo

文件：879.06 Kbytes 页数：33 Pages

ISSI

矽成半导体

2Mx18, 1Mx36 36Mb QUADP (Burst 4) SYNCHRONOUS SRAM

FEATURES  1Mx36 and 2Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface fo

文件：879.06 Kbytes 页数：33 Pages

ISSI

矽成半导体