IS61QDPB251236C中文资料矽成半导体数据手册PDF规格书

FEATURES

 512Kx36 and 1Mx18 configuration available.

 On-chip Delay-Locked Loop (DLL) for wide data valid window.

 Separate independent read and write ports with concurrent read and write operations.

 Synchronous pipeline read with EARLY write operation.

 Double Data Rate (DDR) interface for read and write input ports.

 2.5 Cycle read latency.

 Fixed 2-bit burst for read and write operations.

 Clock stop support.

 Two input clocks (K and K#) for address and control registering at rising edges only.

 Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.

 Data valid pin (QVLD).

 +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.

 HSTL input and output interface.

 Registered addresses, write and read controls, byte writes, data in, and data outputs.

 Full data coherency.

 Boundary scan using limited set of JTAG 1149.1 functions.

 Byte Write capability.

 Fine ball grid array (FBGA) package option:

13mmx15mm and 15mmx17mm body size

165-ball (11 x 15) array

 Programmable impedance output drivers via 5x user-supplied precision resistor.

 ODT (On Die Termination) feature is supported optionally on data input, K/K#, and BWx#.

 The end of top mark (C/C1/C2) is to define options.

IS61QDPB251236C : Don’t care ODT function and pin connection

IS61QDPB251236C1: Option1

IS61QDPB251236C2: Option2

Refer to more detail description at page 6 for each

ODT option.