1Mx18, 512Kx36 18Mb QUAD (Burst 4) SYNCHRONOUS SRAM

FEATURES  512Kx36 and 1Mx18 configuration available.  On-chip Delay-Locked loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface

文件：811.89 Kbytes 页数：31 Pages

ISSI

矽成半导体

1Mx18, 512Kx36 18Mb QUAD (Burst 4) SYNCHRONOUS SRAM

FEATURES  512Kx36 and 1Mx18 configuration available.  On-chip Delay-Locked loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface

文件：811.89 Kbytes 页数：31 Pages

ISSI

矽成半导体

1Mx18, 512Kx36 18Mb QUAD (Burst 4) SYNCHRONOUS SRAM

FEATURES  512Kx36 and 1Mx18 configuration available.  On-chip Delay-Locked loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface

文件：811.89 Kbytes 页数：31 Pages

ISSI

矽成半导体

1Mx18, 512Kx36 18Mb QUAD (Burst 4) SYNCHRONOUS SRAM

FEATURES  512Kx36 and 1Mx18 configuration available.  On-chip Delay-Locked loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface

文件：811.89 Kbytes 页数：31 Pages

ISSI

矽成半导体