1Mx18, 512Kx36 18Mb QUAD (Burst 2) Synchronous SRAM

FEATURES  512Kx36 and 1Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with EARLY write operation.  Double Data Rate (DDR) interface

文件：933.86 Kbytes 页数：29 Pages

ISSI

矽成半导体

1Mx18, 512Kx36 18Mb QUAD (Burst 2) Synchronous SRAM

FEATURES  512Kx36 and 1Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with EARLY write operation.  Double Data Rate (DDR) interface

文件：933.86 Kbytes 页数：29 Pages

ISSI

矽成半导体

1Mx18, 512Kx36 18Mb QUAD (Burst 2) Synchronous SRAM

FEATURES  512Kx36 and 1Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with EARLY write operation.  Double Data Rate (DDR) interface

文件：933.86 Kbytes 页数：29 Pages

ISSI

矽成半导体

1Mx18, 512Kx36 18Mb QUAD (Burst 2) Synchronous SRAM

FEATURES  512Kx36 and 1Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with EARLY write operation.  Double Data Rate (DDR) interface

文件：933.86 Kbytes 页数：29 Pages

ISSI

矽成半导体