IS61NVP409618B-166B3L中文资料矽成半导体数据手册PDF规格书

FEATURES

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single R/W (Read/Write) control pin

• Clock controlled, registered address,

data and control

• Interleaved or linear burst sequence control using

MODE input

• Three chip enables for simple depth expansion

and address pipelining

• Power Down mode

• Common data inputs and data outputs

• CKE pin to enable clock and suspend operation

• JEDEC 100-pin TQFP, 165-ball PBGA and 119-

ball PBGA packages

• Power supply:

NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%)

NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%)

NVVP: Vdd 1.8V (± 5%), Vddq 1.8V (± 5%)

• JTAG Boundary Scan for PBGA packages

• Industrial temperature available

• Lead-free available