IS61NVP25618A-200TQ中文资料北京矽成数据手册PDF规格书

DESCRIPTION

The 4 Meg NLP/NVP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, no wait state, device for networking and communications applications. They are organized as 128K words by 32 bits, 128K words by 36 bits, and 256K words by 18 bits, fabricated withISSIs advanced CMOS technology.

FEATURES

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single R/W (Read/Write) control pin

• Clock controlled, registered address, data and control

• Interleaved or linear burst sequence control using MODE input

• Three chip enables for simple depth expansion and address pipelining

• Power Down mode

• Common data inputs and data outputs

• CKE pin to enable clock and suspend operation

• JEDEC 100-pin TQFP, 165-ball PBGA and 119-ball PBGA packages

• Power supply:

NVP: VDD 2.5V (± 5), VDDQ 2.5V (± 5)

NLP: VDD 3.3V (± 5), VDDQ 3.3V/2.5V (± 5)

• Industrial temperature available

• Lead-free available