IS61NLP51232B中文资料矽成半导体数据手册PDF规格书

FEATURES

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single R/W (Read/Write) control pin

• Clock controlled, registered address, data and control

• Interleaved or linear burst sequence control using MODE input

• Three chip enables for simple depth expansion and address pipelining

• Power Down mode

• Common data inputs and data outputs

• /CKE pin to enable clock and suspend operation

• JEDEC 100-pin QFP, 165-ball BGA and 119-ball BGA packages

• Power supply:

NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)

NVP: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)

NVVP: VDD 1.8V (± 5%), VDDQ 1.8V (± 5%)

• JTAG Boundary Scan for BGA packages

• Commercial, Industrial and Automotive (x36) temperature support

• Lead-free available

• For leaded option, please contact ISSI.