2M x 36 and 4M x 18 72Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi

文件：1.48776 Mbytes 页数：39 Pages

ISSI

矽成半导体

2M x 36 and 4M x 18 72Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi

文件：1.48776 Mbytes 页数：39 Pages

ISSI

矽成半导体

2M x 36 and 4M x 18 72Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi

文件：1.48776 Mbytes 页数：39 Pages

ISSI

矽成半导体

2M x 36 and 4M x 18 72Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi

文件：1.48776 Mbytes 页数：39 Pages

ISSI

矽成半导体