36Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi

文件：1.41526 Mbytes 页数：38 Pages

ISSI

矽成半导体

Package：165-TBGA；包装：托盘 类别：集成电路（IC） 存储器 描述：IC SRAM 36MBIT PARALLEL 165TFBGA

ISSI, Integrated Silicon Solution Inc

Package：165-TBGA；包装：托盘 类别：集成电路（IC） 存储器 描述：IC SRAM 36MBIT PARALLEL 165TFBGA

ISSI, Integrated Silicon Solution Inc

36Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi

文件：1.41526 Mbytes 页数：38 Pages

ISSI

矽成半导体

36Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi

文件：1.41526 Mbytes 页数：38 Pages

ISSI

矽成半导体

36Mb, PIPELINE NO WAIT STATE BUS SRAM

FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control usi

文件：1.41526 Mbytes 页数：38 Pages

ISSI

矽成半导体