IS61LV6432-117PQ中文资料ICSI数据手册PDF规格书

DESCRIPTION

The ICSI IS61LV6432 is a high-speed, low-power synchronous static RAM designed to provide a burstable, high-performance, secondary cache for the Pentium™, 680X0™, and PowerPC™ microprocessors. It is organized as 65,536 words by 32 bits, fabricated with ICSIs advanced CMOS technology.

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and control

• Pentium™ or linear burst sequence control using MODE input

• Three chip enables for simple depth expansion and address pipelining

• Common data inputs and data outputs

• Power-down control by ZZ input

• JEDEC 100-Pin LQFP and PQFP package

• 3.3V VCC and 2.5V VCCQ for 2.5 I/Os

• Two Clock enables and one Clock disable to eliminate multiple bank bus contention.

• Control pins mode upon power-up: – MODE in interleave burst mode – ZZ in normal operation mode

These control pins can be connected to GNDQ or VCCQ to alter their power-up state

• Industrial temperature available